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A bus analyzer is a computer bus analysis tool, often a combination of hardware and software, used during development of hardware or device drivers for a specific bus, for diagnosing bus or device failures, or reverse engineering. A bus analyzer is a type of protocol analyzer, which is designed for use with certain specific parallel and serial bus architectures. It differs from packet analyzers which analyze traffic running across non-bus-based mediums such as Ethernet networks and wireless LANs or PANs. The bus analyzer monitors the bus traffic and decodes and displays the data. It is essentially a logic analyzer with some additional knowledge of the underlying bus traffic characteristics. One of the key differences between a bus analyzer and a logic analyzer is notably its ability to filter and extract only relevant traffic that occurs on the analyzed bus. Some advanced logic analyzers present data storage qualification options that also allow to filter bus traffic, enabling bus analyzer-like features.〔In such a case, it is also sometimes referred to as 'digital bus logger'. This is a kind if data logger that implements a sampling mechanism and a filtering mechanism to extract the traffic that relates to a specific or user-defined protocol. See for example this (digital data logger )〕 Some key differentiator between bus and logic analyzers are: :1. Cost: Logic analyzers usually carry higher prices than bus analyzers. The converse of this fact is that a logic analyzer can be used with a variety of bus architectures, whereas a bus analyzer is only good with one architecture. :2. Targeted Capabilities and Preformatting of data: A bus analyzer can be designed to provide very specific context for data coming in from the bus. Analyzers for serial buses like USB for example take serial data that arrives as a serial stream of binary 1s and 0s and displays it as logical packets differentiated by chirp, headers, payload etc... :3. From a user's perspective, a (greatly) simplified viewpoint may be that developers who want the most complete and most targeted capabilities for a single bus architecture may be best served with a bus analyzer, while users who work with several protocols in parallel my be better served with a Logic Analyzer that is less costly than several different bus analyzers and enables them to learn a single user interface vs several. Analyzers are now available for virtually all existing computer bus standards and form factors such as PCI, CompactPCI, PCI Express, PMC, USB, VMEbus, CANbus and LINbus, etc. Bus analyzers are used in the Avionics industry to analyze MIL-STD-1553, ARINC 429, AFDX, and other avionics databus protocols. Specialized bus analyzers are also used in the mass storage industry to analyze popular data transfer protocols between computers and drives. These cover popular data buses like SATA, SAS, ATA/PI, SCSI, etc. These devices are typically connected in series between the host computer and the target drive, where they 'snoop' traffic on the bus, capture it and present it in human-readable format. For many bus architectures like PCI Express, PCI, SAS, SATA, USB and so on, Analyzers are often used in conjunction with a "Bus Exerciser", which actively engages the bus while the analyzer snoops it. Especially with these bus architectures (PCI and PCI-Express), manufacturers have bundled these functions together into a "Bus Analyzer/Exerciser" that resides on a single board or integrated set of boards. These devices make it possible to generate bad bus traffic as well as good so that the device error recovery systems can be tested. They are also often used to verify compliance with the standard to ensure interoperability of devices since they can reproduce known scenarios in a repeatable way. == See also == *JTAG (boundary scan) 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Bus analyzer」の詳細全文を読む スポンサード リンク
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